User:Clemenzi/Books/CE PE Exam Study Guide II - Part 2
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Computer Engineering PE Exam Study Guide II - Part 2[edit]
Hardware and Test[edit]
- Hardware
- Logic family
- Multi-level cell
- Flip-flop (electronics)
- Race condition
- Binary decision diagram
- Circuit minimization for Boolean functions
- Karnaugh map
- Quine–McCluskey algorithm
- Integrated circuit design
- Programmable Logic
- Standard cell
- Programmable logic device
- Field-programmable gate array
- Complex programmable logic device
- Application-specific integrated circuit
- Logic optimization
- Register-transfer level
- Floorplan (microelectronics)
- Hardware description language
- VHDL
- Verilog
- Electronic design automation
- Espresso heuristic logic minimizer
- Routing (electronic design automation)
- Static timing analysis
- Placement (EDA)
- Power optimization (EDA)
- Timing closure
- Design flow (EDA)
- Design closure
- Rent's rule
- Processors
- Computer architecture
- Harvard architecture
- Processor design
- Central processing unit
- Arithmetic logic unit
- CPU cache
- Instruction set
- Orthogonal instruction set
- Classic RISC pipeline
- Reduced instruction set computing
- Instruction-level parallelism
- Instruction pipeline
- Hazard (computer architecture)
- Bubble (computing)
- Superscalar
- Parallel computing
- Dynamic priority scheduling
- Amdahl's law
- Benchmark (computing)
- Moore's law
- Computer performance
- Supercomputer
- Redundancy & Reliability
- Dependability
- Active redundancy
- Dual modular redundancy
- Triple modular redundancy
- High-availability Seamless Redundancy
- N-version programming
- RAID
- Fault tolerance
- Fault-tolerant computer system
- Watchdog timer
- Redundant array of independent memory
- Memory
- Computer data storage
- Memory controller
- Memory management unit
- Static random-access memory
- Dynamic random-access memory
- Synchronous dynamic random-access memory
- DDR2 SDRAM
- Flash memory
- Memory scrubbing
- Data striping
- Hard disk drive performance characteristics
- Disk sector
- Assembly/Test
- Design rule checking
- SystemVerilog
- In-circuit test
- Joint Test Action Group
- Boundary scan
- Boundary scan description language
- Test bench
- Ball grid array
- Head in pillow (metallurgy)
- Pad cratering
- Land grid array